In a conventional sampling mixer, a filter effect is obtained in a switched capacitor built in a sampling circuit by sampling a signal which is subjected to digital conversion in the sampling circuit (see, for example, Patent Document 1). The sampling mixer disclosed in Patent Document 1 will be described below with reference to the drawings.
FIG. 15 is a circuit diagram of sampling mixer 700 disclosed in Patent Document 1.
In FIG. 15, sampling mixer 700 has TA (transconductance amplifier) 1 that converts the received radio frequency (RF) signal into RF current iRF, in-phase sampling mixer 2 that samples RF current iRF converted by TA 1, reverse phase sampling mixer 3 that is combined with in-phase sampling mixer 2 and DCU (digital control unit) 4 that generates control signals for in-phase sampling mixer 2 and reverse phase sampling mixer 3.
In-phase sampling mixer 2 has sampling switch 5 composed of the FET and Ch (history capacitor) 6 that continues integrating in the time domain the signal sampled by this sampling switch 5. Further, in-phase sampling mixer 2 has a plurality of Cr (rotate capacitor) 7, 8, 9, 10, 11, 12, 13 and 14 that repeat integration and release of the signal sampled in sampling switch 5 and Cb (buffer capacitor) 15 that buffers signals released from rotate capacitors 7 to 14.
Further, in-phase mixer 2 has dump switch 16 for releasing the signals held in Cr 7 to 14 to Cb 15, reset switch 17 that resets signals held in Cr 7 to 14 after signal release and a plurality of integration switches 18, 19, 20, 21, 22, 23, 24 and 25 for sequentially connecting Ch 6 with Cr 7 to 14. Furthermore, in-phase mixer 2 has a plurality of release switches 26, 27, 28, 29, 30, 31, 32 and 33 for sequentially connecting Cr 7 to 14 with Cb 15 and feedback switch 34 that controls an input of a feedback signal from a DA (digital-to-analogue) converter to sampling mixer 700.
Dump switch 16, reset switch 17, integration switches 18 to 25, release switches 26 to 33 and feedback switch 34 are each composed of the n-type FET. The n-type FET is turned on when the gate voltage shows the high level and is turned off when the gate voltage shows the low level. Further, reverse phase mixer 3 is composed in the same way as in-phase mixer 2.
DCU 4 is connected to the gates of integration switches 18 to 25, release switches 26 to 33, dump switch 16, reset switch 17 and feedback switch 34. DCU 4 outputs various control signals to the gates of these switches 16 to 34.
Types of control signals include the SV0 signal to SV7 signal, SAZ signal, SBZ signal, D signal, R signal and F signal. The SV0 signal to SV7 signal operate as the gate signals for applicable integration switches 18 to 25. The SAZ signal operates as the gate signal for release switches 30 to 33 and the SBZ signal operates as the gate signal for release switches 26 to 29.
The D signal operates as the gate signal for dump switch 16 and the R signal operates as the gate signal for reset switch 17. The F signal operates as the gate signal for feedback switch 34.
FIG. 16 shows a timing chart of the control signals generated in DCU 4.
As shown in FIG. 16, the LO signal is a periodic rectangular pulse, and, when the LO signal rises after a predetermined cycle, the SV0 signal to SV7 signal repeat rising and falling alternately.
Then, when the SV0 signal and the SV4 signal rise, the states of the SAZ signal and the SBZ signal are inverted.
The D signal rises when the SV0 signal and SV4 signal rise. On the other hand, the D signal falls when the SV1 signal and SV5 signal fall.
The R signal rises when the D signal falls. Further, the F signal rises when the R signal falls.
Next, referring to the timings of the above control signals, the operation of sampling mixer 700 will be described. The operation of in-phase mixer 2 will be described in detail as an example.
First, TA 1 converts the RE signal into RF current iRF and supplies this RF current iRF to in-phase sampling mixer 2. Then, in-phase mixer 2 samples supplied RF current iRF using the LO signal. The LO signal has virtually the same frequency as RF current iRF. As a result, RF current iRF is discretized in the time domain, and produces discrete signals.
Then, the discrete signals are integrated in Ch 6 and Cr 7 to 14 and filtered and decimated (i.e. decimation). To be more specific, first, the SV0 signal is inputted to the gate of integration switch 18, integration switch 18 is turned on while the SV0 signal shows the high level and Ch 6 is connected to Cr 7. Then, discrete signals are held in Ch 6 and Cr 7. In this case, Cr 7 integrates the discrete signal while the SV0 signal shows the high level (for example, during the eight cycles of the LO signal).
Next, when the SV0 showing the high level falls, the SV1 signal rises at the same time. Then, integration switch 18 is turned off and integration switch 19 is turned on. As a result, Cr 7 is disconnected from Ch 6 and Cr 8 is connected to Ch 6. Then, Ch 6 and Cr 8 hold discrete signals, and Cr 8 integrates the discrete signal while the SV1 signal shows the high level (for example, during eight cycles of the LO signal).
When the SV2 signal to SV7 signal are sequentially inputted to the gates of integration switches 20 to 25, integration switches 20 to 25 are turned on while the SV2 signal to SV7 signal show the high level (for example, during eight cycles of the LO signal). Then, Cr 9 to 14 are sequentially connected to Ch 6, and Cr 9 to 14 integrate discrete signals during, for example, eight cycles of the LO signal.
By so doing, it is possible to produce an effect of an eight-tap FIR (Finite Impulse Response) filter. The sampling rate in this case is decimated to a one-eighth, because signals matching eight cycles of the LO signal are moved, held in eight integration switches 18 to 25 and averaged. A filter configured this way will be referred to as “first step FIR filter.”
Further, Ch 6 sequentially connected with Cr 7 to 14 holds output potential, so that it is possible to produce an effect of an IIR (Infinite Impulse Response) filter. A filter configured this way will be referred to as “first step IIR filter.”
Further, when the above-described SAZ signal is inputted to release switches 26 to 33, all release switches 26 to 33 are turned on while the SAZ signal shows the high level. Then, the discrete signals integrated in Cr 7 to 10 are released to Cb 15 at the same time through release switches 26 to 33 that are turned on.
After this release, next, the D signal shows the low level, dump switch 16 is turned off and Cb 15 is disconnected from Cr 7 to 10.
Next, the R signal shows the high level, reset switch 17 is turned on and signals held in Cr 7 to 10 are reset.
By so doing, signals integrated in Cr 7 to 10 are released to Cb 15 at the same time, so that it is possible to produce an effect of a four-tap FIR filter. The sampling rate in this case is decimated to a one-fourth, because signals integrated by four Cr 7 to 10 is moved and averaged by Cb 15.
Further, signals integrated by Cr 11 to 14 function similar to the case of Cr 7 to 10 and are released to Cb 15 at the same time while the SBZ signal shows the high level. Consequently, it is possible to produce an effect of a four-tap FIR filter. Further, the sampling rate is decimated to a one-fourth. A filter configured this way will be referred to as “second step filter.”
Further, when the SAZ signal shows the high level and the SBZ signal shows the low level, if the R signal is inputted to the gate of reset switch 17 and reset switch 17 is turned on, signals held in four Cr 7 to 10 are released to the ground terminal end of Cr 7 to 10 and reset. On the other hand, when the SBZ signal shows the high level and the SAZ signal shows the low level, if the R signal is inputted to the gate of reset switch 17 and reset switch 17 is turned on, signals held in four Cr 11 to 14 are released to the ground terminal end of Cr 11 to 14 and are reset.
Then, when the F signal is inputted to the gate of feedback switch 34 and feedback switch 34 is turned on, a feedback signal is inputted to sampling mixer 700 from a signal processor through a DA converter (not shown). The feedback signal refers to a signal for compensating for the DC offset or differential offset, and is generated in the signal processor (not shown). To be more specific, the signal processor receives as input the output signal of sampling mixer 700 through the AD converter. Then, the signal processor generates the above-described feedback signal based on this output signal and inputs the feedback signal to sampling mixer 700 through the DA converter. By this means, the DC offset and differential offset are compensated for. By means of the feedback signal in this case, the DC offset and differential offset are compensated for upon the operation of the first step IIR filter.
Further, four Cr are connected to Cb 15 in the above-described unit of a group of four Cr 7 to 10 or a group of four Cr 11 to 14. By this means, it is possible to produce an effect of an IIR filter. A filter configured this way will be referred to as “second step IIR filter.”
Further, reverse phase sampling mixer 3 operates in virtually the same way as in-phase sampling mixer 2 except the following.
That is, the LOB signal operating as the gate signal for sampling switch 35 of reverse phase sampling mixer 3 has 180 degrees of phase difference from the LO signal, and the sampling timing in reverse phase sampling mixer 3 is delayed by half of the cycle, from the timing in in-phase sampling mixer 2.
If sampling mixer 700 is configured this way, the output signal of sampling mixer 700 becomes a signal that has passed through the first step FIR filter, first step IIR filter, second step FIR filter and second step IIR filter.
Next, filter characteristics including the above-described various filters will be described with reference to FIG. 17. Assume that the LO signal frequency is 2.4 GHz, Ch 6 is 15 pF, Cr 7 to 14 are 0.5 pF, Cb 15 is 15 pF and the transconductance of TA 1 is 7.5 mS.
FIG. 17A shows characteristics of the first step FIR filter and FIG. 17B shows characteristics of the first step IIR filter. Further, FIG. 17C shows characteristics of the second step FIR filter, and FIG. 17D shows characteristics of the second step IIR filter. Then, FIG. 17E shows overall filter characteristics of sampling mixer 700. According to this FIG. 17E, the notches (zero points) of overall sampling mixer 700 are formed with the notches of the first step FIR filter (see FIG. 17A) and the notches of the second step IIR filter (see FIG. 17C).
In sampling mixer 700 configured this way, a signal that has passed through four filters, that is, through the first step FIR filter, first step IIP filter, second step FIR filter and second step IIR filter, is inputted to the AD converter.    Patent Document 1: Japanese Patent Application Laid-Open No. 2004-289793 (page 6 to 9, FIG. 3a, FIG. 3b and FIG. 4)